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Low Power Design

Think Silicon can offer design services and consultancy on low power design:

• Block Clock Gating: A very common and simple to implement method for reducing the power consumption. Quite simple the clock is gate on blocks of the chip that are not used. As CMOS circuits typically consume power when their make state transition, cutting the clock for a sub-module will limit the power consumption on the clock network and any possible toggling inside the module. About 1/3 of the dynamic power is consumed on the Clock-Tree. For example if your chip has a UART that you don't use just cut the clock. If the there is no necessity for a clock, just mute it. (Expect 30% reduction on dynamic consumption)

• Dynamic Clock Gating: Dynamic clock gating is like Block Clock gating but the clock gaters are enabled/disabled dynamically in real time during operation. The concept is that if a register will not change it's value, then there is no point in supplying a clock. Dynamic Clock gaters can be inserted in system during synthesis by the Synthesis tool. Special attention must be made during test mode to ensure clock gaters are open during manufacture test. Dynamic clock gating can benefit even active modules where Block Clock gating cannot be used. (Expect a 10% reduction on this block)

• MultiVT (Multiple Voltage Threshold): It is quite common in 130nm and below libraries to be two sets of cells that operate different voltage threshold. Thus there are the fast but high leakage cells and the slower but low leakage cells. The good thing about this technology is that these two types of cells can be mixed in a design. Therefore you can have the gates on the timing critical path using high-leakage gates, but all the rest of the gates in low-leakage.

• Multivoltage (Mvdd), Voltage Islands and Voltage Throttling and Power Gating: The Critical paths of a system will require the maximum allowed voltage to meet timing. However, on the non-timing critical parts of the chip, the device can operate at a lower voltage and still meet the timing, thus reducing both the dynamic and leakage power consumption for this block. You will be required to put level-shifters between blocks that are running at different voltages and can use isolation cells to shut-down any voltage-domain. The creation of voltage islands will require the voltage shifter and isolation cells when the module is completely turned-off However special attention must be paid for the voltage regulator and if dynamic voltage throttling is required. Sign-off STA can becoming quite complicated in choosing the correct test corners.

• Frequency Throttling: Another technique to limit dynamic power is frequency throttling. For example, when your networking chip is sitting idle waiting for network packets to come, there is not point in clocking it at maximum frequency to execute NOP loops and just waiting for interrupts. Frequency throttling can be used to change the dynamically the frequency of operation according the the load of the device.

• Memory (Reduction of both dynamic and leakage power): In low geometry technologies is quite common for memories to be power-aware. Memory cell or blocks can either be completely shut-down to save memory use. These memories can use the multiVT method described above to achieve better power consumption. Power aware Memories can also be set into a sleep mode where the contents are preserved.

• Logic Techniques to limit power: Advanced Synthesis programs that use dynamic and leakage power as a optimisation parameters can use many of these logic tricks to limit the usage of memories.

  • Gray Counters. If your systems uses a counter, if you use a binary gray encoded counter you will have less state transitions, therefore limiting the dynamic power consumption.

  • Avoid Glitches. If your system has a lot of glitches, then you have a lot more state transitions than you think, therefore you consume a lot more energy than necessary.

  • Operand Isolation. If your example you have a complex multiplier in your system and your logic optimisation is set to allow values to propage through even when your multiplier is not in use, then you use more power supply than you need. You can use operand isolation to set inputs at a Constant value when this particular piece of logic is not needed.

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