Generator

Fraction bits
Exponent bits
Sign
Language	Verilog

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Documentation

Floating Poing Adder/Subtractor

• IEEE-754 Single Precision (32bits)
  
• Supports Round-to-nearest
• Supports Denormals
• pure Verilog rtl
• Synthesizable
  

FP AddSub datasheet

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History

Revision history

 Version v1.00

License

License : TSi_FPU

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For further information please contact sales@ipgeniuscores.com