Generator

The VXL Viterbi Decoder IP core implements the Viterbi algorithm for decoding a bitstream encoded by a corresponding Forward Error Correction convolutional encoding system. A lot of digital communication systems incorporate a Viterbi decoder for decoding convolutionally encoded data. By using the minimum likelihood algorithm, the Viterbi decoder core is able to correct errors in received data caused by channel noise. The decoded output data is equivalent to the transmitted digital data stream.

For further information please contact sales@ipgeniuscores.com

Documentation

Overview:

The VXL Viterbi Decoder IP core implements the Viterbi algorithm for decoding a bitstream encoded by a corresponding Forward Error Correction convolutional encoding system. A lot of digital communication systems incorporate a Viterbi decoder for decoding convolutionally encoded data. By using the minimum likelihood algorithm, the Viterbi decoder core is able to correct errors in received data caused by channel noise. The decoded output data is equivalent to the transmitted digital data stream.

Features

Industry standard constraint length 7, rate = ½, (G0, G1) = (171, 133)

High output data rates of up to 45 Mbps

Low latency of 111 clocks.

Parallel architecture design

Trace-back logic for continuous decoding

Trace back length of 35

Soft decision decoding

Fully synchronous design

Key Benefits:

Small silicon footprint

High throughput/data rates

Low latency

Bit equivalent Matlab Model available

Elaborate Test bench.

Parameterizable HDL core design

RTL source code available for easy integration and implementation

Viterbi Decoder IP core

For further information please contact sales@ipgeniuscores.com

History

Revision history

 Version v1.00

License

License : VXL

For further information please contact sales@ipgeniuscores.com