Generator

The VXL parameterizable Reed-Solomon, RS (255, 239) IP core is optimized in terms of speed and area. The core is available for Xilinx Spartan and Virtex series FPGAs. ASIC standard cell libraries flow is also provided according to customer request.

For further information please contact sales@ipgeniuscores.com

Documentation

Overview:

The VXL parameterizable Reed-Solomon, RS (255, 239) IP core is optimized in terms of speed and area. The core is available for Xilinx Spartan and Virtex series FPGAs. ASIC standard cell libraries flow is also provided according to customer request.

Features:

Standard configuration RS(255, 239)

OTN G.709 compliant implementation

255-symbol block size

8-bit symbol size

Synchronous single clocked pipeline design

Continuous data flow operation

No gaps between code blocks

Count of corrected error symbols (when less than or equal to 8)

Detection of error symbols (when more that 8)

Key Benefits:

Small silicon footprint

High speed capabilities

Easily modifiable to implement different Reed-Solomon coding standards

Parameterizable design

FPGA proven for Xilinx Virtex and Spartan series FPGA

ASIC standard flow also supported according to customer needs

RTL source code available for easy integration and implementation

Reed Solomon (RS) Codec

For further information please contact sales@ipgeniuscores.com

History

Revision history

 Version v1.00

License

License : VXL

For further information please contact sales@ipgeniuscores.com