Generator

The JPEG 2000 IP core is a JPEG 2000-ISO/IEC 15444-1 compliant encoder. The JPEG 2000 operates on a single clock domain and it can be easily integrated into any multimedia system. A synchronous Reset signal is also provided. The core is efficiently designed, synthesized for Xilinx FPGA target technology and thoroughly verified. The JPEG 2000 IP core is available in VHDL RTL source code.

Bits per Pixel:	8-bits10-bits12-bits
Encoding:	Lossy (9/7) DWTLossless (5/3) DWT

For further information please contact sales@ipgeniuscores.com

Documentation

Overview:

The JPEG 2000 IP core is a JPEG 2000-ISO/IEC 15444-1 compliant encoder. The JPEG 2000 operates on a single clock domain and it can be easily integrated into any multimedia system. A synchronous Reset signal is also provided. The core is efficiently designed, synthesized for Xilinx FPGA target technology and thoroughly verified. The JPEG 2000 IP core is available in VHDL RTL source code.

Features:

JPEG2000-ISO/IEC 15444-1 standard compliant

User selectable lossless and lossy compression

Rate Control

Programmable bit rate up to 10 bits per sample

Programmable image/tile size up to 8192 x 512

JPEG2000 graphics file format (.j2k) output

Large Frames Processing without unpleasant Blocking Artifacts

Fairly brisk input pixel rate in excess of 100 MSamples/Sec

Fully synchronous single clock design

Internal Memory System architecture

Key Benefits:

Low target device memory and logic silicon footprint

Motion JPEG support available (optional)

Bit equivalent C model provided

Parameterizable HDL design

Easily modifiable design to meet specific requirements

Available for Xilinx Virtex-4 & 5 series FPGA devices

RTL source code available for easy integration and implementation

JPEG 2000 Encoder IP Core

For further information please contact sales@ipgeniuscores.com

History

Revision history

 Version v1.00

License

License : VXL

For further information please contact sales@ipgeniuscores.com