Generator

No. of Channels
AHB Slave Register File
Language	Verilog

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Documentation

DMA Engine Features

• AMBA AHB 2.0 compliant
• Configurable DMA transfers
• AHB to AHB
• AHB to FIFO
• FIFO to AHB
• Configurable number of channels
• Configurable FIFO size
• AMBA AHB Slave Interface for register programming
• AMBA AHB Master Interface(s) for DMA transfers
• FIFO access Interface(optional) for DMA transfers
• One FIFO per channel
• Different Clock Domains at FIFO side and AHB side
• AMBA AHB Master supports burst transfers
• Byte alignment supported
• Direct Access to FIFO data
• Programmable Interrupt lines

TSi DMAC datasheet

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AMBA is a registered trademark of ARM Limited. AXI, AHB, AHB-Lite, APB, ATB and ASB are trademarks of ARM Limited.

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History

Revision history

Version v1.00

License

License : TSi_DMAC

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